Full-wave solving is experimental and off by default | method | Full-wave solving works — a board solves end to end and the field maps come back — but none of it has been checked against a real board, and no run has been made at the record length a radiated result needs (30 MHz means 100 ns of simulated time, millions of timesteps). Until that is done, full-wave solving and everything built on it (hotspot maps, the far field, cable emissions and the compliance estimate) is switched off unless a server enables it with EMI_EXPERIMENTAL=full-wave. The geometric checks, the ESD simulation and the cable budget do not use it. |
Only comparisons between board versions are reliable | method | Comparing two versions of the same board gives a reliable result, for example that one layout radiates 8 dB less than another at 480 MHz, and which trace causes the difference. Modelling errors largely cancel between two runs of the same design, so a comparison remains valid despite the other limitations on this page. Absolute field strengths do not. Treat any single value as an order-of-magnitude estimate, not as a measurement. |
Whole-board solves are not supported | hard | A 100 × 80 mm board meshed at 25 µm has about 1.9 billion cells. That requires about 138 GB of memory and roughly ten weeks of computation. A graded mesh reduces this to about two weeks. Analysis therefore runs on a region that you select. This is a limit of the FDTD method, not of this implementation. |
Cables are modelled separately from the board, and only as a budget | hard | Below about 300 MHz, most emission failures are caused by common-mode current on an attached cable harness, which acts as the antenna. A full-wave solve contains only the board and cannot show that. The Cables tab covers it separately: each declared cable is modelled as a wire over a ground plane, and the result is a budget — how much common-mode current that cable can carry before it reaches a limit — not a prediction of what it does carry. A connector you do not declare is not modelled at all. |
The useful frequency range is about 100 MHz to 3 GHz | band | To resolve the lowest frequency of interest, the simulation must run for 3 / f_min. The timestep is set by the smallest mesh cell, which is around 0.05 ps for PCB features. Resolving 30 MHz therefore needs several hundred thousand additional timesteps, and emissions in that range are usually dominated by cable effects. |
Results are relative unless you supply a driver spectrum | setup | openEMS simulates passive structures. It calculates how the layout responds to an excitation, but it has no information about the signals on your board, such as a buck converter switching 3 A in 4 ns. Absolute field strengths require a defined source: a declared edge rate and amplitude, or a measured switching edge. |
Components are not modelled | setup | ICs, connectors and decoupling capacitors are represented only by their copper geometry, unless lumped models are provided. Package parasitics dominate above about 1 GHz, so results in that range describe the bare board and not the assembled board. |
Stackup material values must be correct | setup | Permittivity and loss tangent depend on frequency and on the fabricator. If your board file does not include them, FR-4 values are used and marked "assumed" in the stackup panel. An incorrect εr shifts every resonance in the result. |
Mesh resolution limits accuracy | method | FDTD uses a rectilinear grid, so curved and angled copper is approximated in steps. A finer mesh reduces this error. Each halving of the cell size costs roughly four times as much computation. |
Immunity checks are layout rules, not an immunity test | method | The ESD, shield and reset-line checks look for the layout mistakes behind most IEC 61000-4-2 and 61000-4-4 failures, from how parts are placed and connected. Nothing is injected or simulated, so they cannot say what discharge or burst level a board survives. Parts are recognised by reference designator, value and footprint: a protection device the tool does not recognise is reported as missing, and a connector counts as I/O by how close it sits to the board edge. |
ESD simulation voltages are estimates; compare them | method | The simulation models the trace, the clamp and its ground via from the layout, but an IC's internal protection is not published, so every pin is the same generic CMOS input. Absolute volts at a pin are therefore estimates. What holds is the comparison between variants of the same line — the clamp where it is against the clamp at the connector. Planes are ideal (no ground bounce or coupling to neighbouring traces), only contact discharge is simulated, and it is injected at a pin, which is the worst case: a test discharges to a metal shell. Uploaded SPICE models replace the datasheet model only after the worker has checked them. |
Board data is stored and processed in the cloud | privacy | Uploaded board files and their results are stored in DigitalOcean Spaces and processed by a worker operated by EmbeddedCI. They are not sent to any third-party service or external solver. The files do leave your network, so handle them as you would any other cloud upload of an unreleased design. |
Results are not a compliance prediction | legal | Where a CISPR limit line is shown, it is a reference for comparing versions of your own board. It is not a pass or fail result, it is not a pre-scan, and it does not replace testing at a test house. |
